image/svg+xmlMotorola 68000 CPU Opcodes
B
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
B
I
0
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
0
W
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
W
I
0
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
0
0
1
B
W
L
0
0
0
0
0
0
0
0
I
0
1
0
0
1
1
1
0
0
1
1
1
0
1
1
0
0
1
0
B
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
B
I
0
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
W
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
W
I
0
1
0
0
1
1
1
0
1
0
1
0
0
B
W
L
0
0
0
0
0
0
1
0
I
0
1
0
0
1
1
1
0
1
1
1
0
1
B
W
L
0
0
0
0
0
1
0
0
I
W
L
0
1
0
0
1
D
0
0
1
S
W
M
1
1
0
B
W
L
0
0
0
0
0
1
1
0
I
L
0
1
0
0
1
1
1
1
1
1
0
1
0
B
0
0
0
0
1
0
1
0
0
0
1
1
1
1
0
0
B
I
W
0
1
0
0
1
1
0
1
1
1
0
1
1
W
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
0
W
I
B
W
L
0
1
0
1
0
1
1
1
0
0
0
B
W
L
0
0
0
0
1
0
1
0
I
B
W
L
0
1
0
1
1
1
1
1
0
0
1
B
W
L
0
0
0
0
1
1
0
0
I
B
0
1
0
1
1
1
1
1
1
1
0
0
B
L
0
0
0
0
1
0
0
0
0
0
B
N
W
0
1
0
1
1
1
0
0
1
W
D
B
L
0
0
0
0
1
0
0
0
0
1
B
N
B
W
0
1
1
0
0
0
0
0
W
D
S
d
D
B
L
0
0
0
0
1
0
0
0
1
0
B
N
B
W
0
1
1
0
0
0
0
1
W
D
0
0
0
1
R
0
B
L
0
0
0
0
1
0
0
0
1
1
B
N
B
W
0
1
1
0
W
D
0
1
0
1
1
L
1
B
L
0
0
0
0
1
0
0
B
N
L
0
1
1
1
0
1
0
1
1
0
B
L
0
0
0
0
1
0
1
B
N
W
1
0
0
0
0
1
1
M
B
L
0
0
0
0
1
1
0
B
N
W
1
0
0
0
1
1
1
0
B
L
0
0
0
0
1
1
1
B
N
B
1
0
0
0
1
0
0
0
0
M
0
0
0
0
1
W
L
0
0
0
0
1
D
S
0
0
1
W
D
B
W
L
1
0
0
0
D
0
0
0
1
W
L
0
0
0
0
1
B
W
L
1
0
0
1
D
0
0
1
0
M
B
W
L
0
0
B
W
L
1
0
0
1
1
0
0
M
0
0
1
1
0
W
0
1
0
0
0
0
0
0
1
1
W
L
1
0
0
1
S
1
1
0
1
0
0
1
B
0
1
0
0
0
1
0
0
1
1
B
W
L
1
0
1
1
1
0
1
0
1
W
0
1
0
0
0
1
1
0
1
1
B
W
L
1
0
1
1
1
0
0
1
0
1
1
0
B
W
L
0
1
0
0
0
0
0
0
B
W
L
1
0
1
1
0
0
1
1
1
B
W
L
0
1
0
0
0
0
1
0
W
L
1
0
1
1
S
1
1
1
0
0
0
B
W
L
0
1
0
0
0
1
0
0
W
1
1
0
0
0
1
1
1
0
0
1
B
W
L
0
1
0
0
0
1
1
0
W
1
1
0
0
1
1
1
1
0
1
0
W
L
0
1
0
0
1
0
0
0
1
S
0
0
0
B
1
1
0
0
1
0
0
0
0
M
1
0
1
1
B
0
1
0
0
1
0
0
0
0
0
L
1
1
0
0
1
0
0
M
1
1
0
0
W
0
1
0
0
1
0
0
0
0
1
0
0
0
B
W
L
1
1
0
0
D
1
1
0
1
L
0
1
0
0
1
0
0
0
0
1
B
W
L
1
1
0
1
D
1
1
1
0
0
1
0
0
1
0
1
0
1
1
1
1
1
1
0
0
B
W
L
1
1
0
1
1
0
0
M
1
1
1
1
B
0
1
0
0
1
0
1
0
1
1
W
L
1
1
0
1
S
1
1
B
W
L
0
1
0
0
1
0
1
0
B
W
L
1
1
1
0
0
0
0
D
1
1
0
1
0
0
1
1
1
0
0
1
0
0
B
W
L
1
1
1
0
0
0
1
D
1
1
W
0
1
0
0
1
1
1
0
0
1
0
1
0
W
D
B
W
L
1
1
1
0
0
1
0
D
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
B
W
L
1
1
1
0
0
1
1
D
1
1
L
0
1
0
0
1
1
1
0
0
1
1
0
D
B
W
L
1
1
1
0
D
M
0
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
0
0
B
W
L
1
1
1
0
D
M
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
B
W
L
1
1
1
0
D
M
1
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
W
I
B
W
L
1
1
1
0
D
M
1
1
D
D
D
0
1
0
1
0
1
M
S
0
0
0
Register to memory
Memory to register
Direction
Dn ♦ <ea> → Dn
<ea> ♦ Dn → <ea>
Direction
Mode
Dn
-(An)
Data Size
Letter
B
W
L
Displacement
Optional Displacement
Register List Mask
Letter
I
N
D
D
M
Direction
Right
Left
Byte
Word
Long
Any
Rotation
Immediate
Register
Plus
Minus
Greater or Equal
Less Than
Greater Than
Less or Equal
Data Type
Immediate
Bit Index
LT
GT
LE
GE
PL
MI
False
Higher
Lower or Same
Carry Clear
Carry Set
Not Equal
Equal
Overflow Clear
Overflow Set
.l
Mnemonic
Addressing Mode
Data register
Address register
Address
Address with Postincrement
Address with Predecrement
Address with Displacement
Address with Index
Program Counter with Displacement
D0
D1
D2
D3
D4
D5
D6
D7
A0
A6
A7
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
A1
A2
A3
A4
A5
Mode
Postincrement
Predecrement
ADDA
ASd
LSd
ROXd
ROd
ASd
LSd
ROXd
ROd
UNLK
MOVE USP
RESET
NOP
STOP
An
An
Register List Mask
A7
A6
A5
A4
SUBQ
Scc
DBcc
BRA
BSR
Bcc
MOVEQ
DIVU
Displacement
Xn
Brief Extension Word
Rotation
Xn
M
S
S
S
Xn
Dn
S
Dn
Dn
S
Xn
RTS
TRAPV
RTR
JSR
JMP
MOVEM
LEA
CHK
ADDQ
Mnemonic
ORI to CCR
ORI to SR
ORI
ANDI to CCR
ANDI to SR
ANDI
SUBI
ADDI
EORI to CCR
EORI to SR
EORI
CMPI
BTST
BCHG
BCLR
BSET
EXT
BTST
BCHG
BCLR
BSET
MOVEP
NBCD
SWAP
PEA
ILLEGAL
TAS
TST
TRAP
LINK
MOVEA
MOVE
MOVE from SR
MOVE to CCR
MOVE to SR
NEGX
CLR
NEG
NOT
S
Xn
Size
Data
reg
S
Cond
Xn
reg
S
An
M
DIVS
SBCD
OR
SUB
Format
Dn
An
(An)
(An)+
-(An)
(d
16
, An)
(d
8
, An, Xn)
Data
S
Size
Single Effective Address Operation Word
Single Effective Address Operation Word
reg
reg
reg
reg
reg
M
(xxx).W
(xxx).L
#imm
Suffix
M
Xn
Dn
Xn
An
M
Xn
Mnemonic
RTE
(d
16
, PC)
(d
8
, PC, Xn)
True
CC
CS
NE
EQ
VC
VS
T
F
HI
LS
Program Counter with Index
Absolute Short
Absolute Long
Immediate
Operation Size
Byte
Word
Long
Condition
.b
.w
M
Rotation
Rotation
Xn
M
Xn
M
Dn
Dn
Dn
Xn
S
Xn
Xn
Displacement
Displacement
M
Xn
M
Xn
Rotation
S
M
Xn
S
M
Xn
Xn
Xn
An
Xn
An
M
Xn
M
Xn
S
M
Xn
Xn
Xn
Xn
Dn
M
Dn
M
Xn
Xn
M
An
M
Xn
S
M
S
An
S
Dn
Dn
M
Xn
M
Xn
Dn
Xn
An
M
Dn
M
M
Xn
M
Xn
S
An
Vector
Condition
Dn
M
SUBX
SUBA
EOR
CMPM
CMP
CMPA
MULU
MULS
ABCD
EXG
AND
ADD
ADDX
M
Xn
Dn
Xn
Data
Displacement
Data
M
Xn
Dn
Data
M
Condition
Xn
M
S
S
Condition
M
Dn
Xn
S
Xn
Dn
M
Xn
M
Xn
S
S
M
Xn
M
Xn
M
Xn
Dn
M
Xn
Xn
Dn
Dn
Dn
Dn
Xn
An
M
M
Xn
M
Xn
M
Xn
S
M
Xn
S
M
Xn
Dn
M
Xn
M
Xn
M
Xn
M
Xn
M
Xn
S
M
Xn
S
M
Xn
S
M
Xn
S
M
Xn
S
M
Xn
S
M
Xn