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author | Aleksey Veresov <aleksey@veresov.pro> | 2021-02-14 21:01:33 +0300 |
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committer | Aleksey Veresov <aleksey@veresov.pro> | 2021-02-14 21:01:33 +0300 |
commit | 0cdd25d921202030745069dbccd16ef856e16750 (patch) | |
tree | e67d27b96bda96d118e61547f23a0a44e567a594 /src/Machine.hs | |
parent | 1ad10fab38c4be9dac68fba9c8249591d883d699 (diff) | |
download | suem-0cdd25d921202030745069dbccd16ef856e16750.tar suem-0cdd25d921202030745069dbccd16ef856e16750.tar.xz suem-0cdd25d921202030745069dbccd16ef856e16750.zip |
Example commands added.
Diffstat (limited to 'src/Machine.hs')
-rw-r--r-- | src/Machine.hs | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/Machine.hs b/src/Machine.hs new file mode 100644 index 0000000..5e6256f --- /dev/null +++ b/src/Machine.hs @@ -0,0 +1,38 @@ +module Machine where + +import qualified Data.Vector.Unboxed as V +import Data.Word +import Data.Bits + +data Registers = Registers { + pc :: Word32, + sr :: Word16, + drs :: [Word32], -- d0 to d7 + ars :: [Word32], -- a0 to a6 + usp :: Word32, -- this is a7 in user mode + ssp :: Word32 -- this is a7 in supermode +} + +data Machine = Machine { + regs :: Registers, + ram :: V.Vector Word8, + rom :: V.Vector Word8 +} + +isSupervisor :: Machine -> Bool +isSupervisor m = testBit (sr $ regs m) 2 + +getByte :: Machine -> Int -> Word8 +getByte m a | a < 0x8 = rom m V.! a + | a < 0x7e0000 = if V.length (ram m) >= a then ram m V.! a + else 0xff + | a < 0x800000 = rom m V.! (a - 0x7e0000) + | otherwise = 0xff + +getWord :: Machine -> Int -> Word16 -- TODO: only even addresses are allowed +getWord m a = (fromIntegral $ getByte m a) * 256 + + (fromIntegral $ getByte m (a + 1)) + +getLong :: Machine -> Int -> Word32 -- TODO: only even addresses are allowed +getLong m a = (fromIntegral $ getWord m a) * 256 * 256 + + (fromIntegral $ getWord m (a + 2)) |