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authorAleksey Veresov <aleksey@veresov.pro>2021-03-22 12:57:05 +0300
committerAleksey Veresov <aleksey@veresov.pro>2021-03-22 12:57:05 +0300
commit433b2173acf1ed838733f58294c0a4286cdce122 (patch)
tree1d2dd118f60d413dee0a89f60e0bb5c9b9d03cbb /src
parent8396f8177d27d2a3a170e9adcc5328b7cfe4d6f9 (diff)
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fix of fix
Diffstat (limited to 'src')
-rw-r--r--src/Machine.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/Machine.hs b/src/Machine.hs
index f28685f..6a09be9 100644
--- a/src/Machine.hs
+++ b/src/Machine.hs
@@ -215,34 +215,34 @@ setTracing b = with sr $ \sr -> do
writeIORef sr $ (if b then setBit else clearBit) srval 0
setSupervisor :: Bool -> Emulator ()
-setSupervisor = with sr $ \sr -> do
+setSupervisor b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 2
-- setInterruptLevel :: Int -> Emulator ()
setExtend :: Bool -> Emulator ()
-setExtend = with sr $ \sr -> do
+setExtend b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 11
setNegative :: Bool -> Emulator ()
-setNegative = with sr $ \sr -> do
+setNegative b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 12
setZero :: Bool -> Emulator ()
-setZero = with sr $ \sr -> do
+setZero b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 13
setOverflow :: Bool -> Emulator ()
-setOverflow = with sr $ \sr -> do
+setOverflow b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 14
setCarry :: Bool -> Emulator ()
-setCarry = with sr $ \sr -> do
+setCarry b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 15