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authorAleksey Veresov <aleksey@veresov.pro>2021-04-07 21:42:34 +0300
committerAleksey Veresov <aleksey@veresov.pro>2021-04-07 21:42:34 +0300
commit5dfcc43bfed0e3db9ec1fdae9dea6eea0c5ca220 (patch)
tree049aa306ff7e26aafea45731913c4febc470d690 /src
parentb1353284f8fc9b40a06856fe2c60a6981538a2fa (diff)
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Interrupt setter added.
Diffstat (limited to 'src')
-rw-r--r--src/Machine.hs12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/Machine.hs b/src/Machine.hs
index 91bcca0..a16127f 100644
--- a/src/Machine.hs
+++ b/src/Machine.hs
@@ -6,7 +6,7 @@ import qualified Data.Vector.Unboxed as V
import qualified Data.Vector.Unboxed.Mutable as VM
import Prelude hiding (Word)
import Data.Word (Word32, Word16, Word8)
-import Data.Bits (testBit, setBit, clearBit)
+import Data.Bits (testBit, setBit, clearBit, (.&.), (.|.), shift)
import Data.IORef
import Control.Monad
import Control.Monad.IO.Class (liftIO)
@@ -191,6 +191,11 @@ incPC = with pc $ \pc -> do
-------------------------------------------------------------------------------
-- Status Register Access
+writeSR :: Word -> Emulator ()
+writeSR v = with sr $ \sr -> do
+ writeIORef sr v
+
+readSR :: Emulator Word
readSR = with sr $ \sr -> do
sr <- readIORef sr
return sr
@@ -247,7 +252,10 @@ setSupervisor b = with sr $ \sr -> do
srval <- readIORef sr
writeIORef sr $ (if b then setBit else clearBit) srval 13
--- setInterruptLevel :: Int -> Emulator ()
+setInterruptLevel :: Int -> Emulator ()
+setInterruptLevel v = do
+ srv <- readSR
+ writeSR $ srv .&. fromIntegral 0xF8FF .|. fromIntegral (shift v 16)
setExtend :: Bool -> Emulator ()
setExtend b = with sr $ \sr -> do