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authorAleksey Veresov <aleksey@veresov.pro>2021-03-21 23:25:05 +0300
committerAleksey Veresov <aleksey@veresov.pro>2021-03-21 23:25:05 +0300
commitd5548c4b4d59370f1cdbc46366be6c265268c465 (patch)
tree18eb918dbc68f58d95d66477391123c8a3b7a173 /src
parentfdbd085148f9f95d0cf5f9acddf9dfb4b67004ad (diff)
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Diffstat (limited to 'src')
-rw-r--r--src/Machine.hs38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/Machine.hs b/src/Machine.hs
index 42e1c60..537c2fc 100644
--- a/src/Machine.hs
+++ b/src/Machine.hs
@@ -209,6 +209,44 @@ isCarry = with sr $ \sr -> do
return $ testBit sr 15
+setTracing :: Bool -> Emulator ()
+setTracing b = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 0
+
+setSupervisor :: Bool -> Emulator ()
+setSupervisor = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 2
+
+-- setInterruptLevel :: Int -> Emulator ()
+
+setExtend :: Bool -> Emulator ()
+setExtend = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 11
+
+setNegative :: Bool -> Emulator ()
+setNegative = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 12
+
+setZero :: Bool -> Emulator ()
+setZero = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 13
+
+setOverflow :: Bool -> Emulator ()
+setOverflow = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 14
+
+setCarry :: Bool -> Emulator ()
+setCarry = with sr $ \sr -> do
+ srval <- readIORef sr
+ writeIORef sr $ (if b then setBit else clearBit) srval 15
+
+
-------------------------------------------------------------------------------
-- Memmory Access